1. Field of the Invention
The present invention relates generally to the field of electrical devices. More particularly, the present invention relates to the field of semiconductor devices.
2. Description of the Related Art
A trend in the computer industry is to integrate more system functions onto a single chip through large scale integration (LSI) and very large scale integration (VLSI) designs. As more and more functions are integrated onto a single chip, chip sizes have generally increased. At the same time, there is a trend in the computer industry towards smaller package outlines (e.g., minimizing plastic packaging) with an emphasis on surface-mount packages.
These two trends inevitably lead to increased mechanical stresses on the plastic package and on the chip itself. For example, the occurrence of cracks from die mounting, deformed metal, passivation cracks, and multi-layer oxide cracks has increased.
Many of these cracks are created by package-induced surface shear stresses. These stresses are most pronounced at chip corners in passivations over wide aluminum buses, in narrow polysilicon interconnects passing under the wide bus, and in the multi-level oxides along the edges of the buses. These stresses can lead to degraded leakage and corrosion performance. In the case of multi-layer oxide cracks, these cracks can cause complete device failure.
Temperature cycle testing is implemented as a phase in the qualification of large plastic-packaged chips due to the above discussed stresses. For example, present qualification guidelines require a device to pass 1,000 cycles of -65.degree. C. to 150.degree. C.
Chip manufacturers have attempted to minimize the above discussed problems in several ways. Several of these methods to minimize shear stress damage to chips are outlined in Texas Instruments Technical Journal, "Shear Stress Damage to Chips: A Design Solution," by Paul Nixon and Darvin Edwards. First, chip manufacturers reserve specific areas in the corners where there are no metal, poly-structures or active circuits therein. Second, chip manufacturers layout metal lines and buses at a 45.degree. angle in corner areas outside the specific area, noted above.
Although all these above-mentioned methods provide limited improvement in the occurrence of die cracking, none of these methods eliminate the failure mode. Moreover, as process techniques for the manufacture of wafers migrate to tighter geometries and smaller feature size devices, the semiconductor die may become more susceptible to die cracking. Thus, there is a need to find a method and apparatus for preventing shear stress damage to a semiconductor chip.